The present invention relates generally to a method and apparatus for programming semiconductor memory devices, and more particularly, to a method and apparatus for interleaving the programming of E.sup.2 ROM memory devices with flash memory devices so as to reduce overall programming time.
Cellular telephones commonly incorporate one or more types of nonvolatile memory devices. For instance, one known configuration employs a flash memory to store a processing program (i.e. the code) used by the cellular telephone, and an EEPROM for storing various configuration parameters and like information (i.e. the non-volatile data segment). U.S. Pat. No. 5,564,032 to Aota et al. exemplifies a cellular telephone which uses both a flash memory and an EEPROM. In the technique taught by Aota, the flash memory is programmed using program code stored in the EEPROM.
The EEPROM (hereinafter referred to as "E.sup.2 ROM" for brevity) and the flash memory are typically programmed with binary data at the factory. For the flash memory, this binary data may represent the executable code used by the cellular phone in performing its various ascribed functions. For the E.sup.2 ROM, this binary data may represent non-volatile variables (e.g. serial number). Alternatively, the E.sup.2 ROM can simply be initialized to all zeros. The programming process is quite time consuming due to the programming requirements of flash memories and E.sup.2 ROMs, and thus creates a significant bottleneck which adds to the cost of manufacturing the cellular telephones.
Notably, programming of a typical flash memory entails a two stage process. In the first stage, a computer processor loads a byte or a page of data into the flash's internal buffer. At the completion of the data load, the flash memory enters a program stage where the flash memory writes the information from its internal data buffer into its flash memory array. The computer processor periodically polls the flash memory during the second stage of programming to determine if the flash is finished programming. Otherwise, the computer processor serves no active role in the second stage of programming. The second stage is typically much longer than the first stage. Thus, the computer processor essentially remains idle for a substantial amount of time during the program cycle. E.sup.2 ROMs are programmed using a similar two-stage approach.
Some practitioners have suggested various ways to reduce the amount of idle time of the processor during programming. U.S. Pat. No. 5,488,711 to Hewitt et al., for example, discloses downloading a burst of data from a computer processor to a static random access memory (SRAM) cache in the memory device, where this information is grouped into a plurality of pages. The SRAM then sequentially feeds pages into rows of an internal EEPROM memory array until the SRAM is depleted. During this sequential feeding operation, the processor is free to perform other tasks.
U.S. Pat. No. 5,530,828 to Kaki et al. teaches another method for reducing idle time of the processor. In this technique, a processor receives requests for writing data to an associated disk pack comprising a plurality of flash memory devices serviced by a write buffer memory. The processor responds to a request by translating logic sector numbers in the request to physical sector numbers associated with areas of the flash memories into which data are to be written. More specifically, the sector numbers are determined such that the data is distributed among a plurality of flash memories. The specific allocation of data among the flash memories is registered in a write management table.
After forming the write management table, the processor downloads the data to the write buffer memory. Information is then transferred from the write buffer memory to respective flash memories. More specifically, a first data block is transmitted to a first respective chip, which then commences to program this data into its internal memory array. While that chip is programming, a second data block is transmitted to a second chip, which then commences programming this data into its memory array. In this manner, this technique overlaps the programming time of two or more flash memories.
While useful, the above described systems do not specifically address the unique problems confronted in programming flash memories and E.sup.2 ROMS in the cellular telephone (or analogous) environment. For instance, the E.sup.2 ROM and flash memory store two respective discrete sets of data files. The E.sup.2 ROM stores the various user defined parameters while the flash memory stores the operating code used by the cellular phone. Unlike Kaki, therefore, the processor in this environment is not free to arbitrarily distribute data from a single binary file to a plurality of flash memories. Rather, each device is loaded with a unique and specific binary file. This constraint presents a number of challenges. For instance, the E.sup.2 ROM may have a different (e.g. smaller) memory capacity than the flash memory device, and may accept information in different size blocks of data. For example, E.sup.2 ROMs may most efficiently accept information in units of pages, whereas flash memory may accept information in units of bytes or pages. The above described documents do not disclose or suggest how to interleave two separate streams of data between two different types of semiconductor memory devices. Nor do the above-described documents disclose or suggest how such interleaving is performed when the memory devices vary in memory capacity and/or storage protocol.
Accordingly it is an exemplary objective of the present invention to provide a technique for initializing semiconductor memory devices which does not suffer from the above described drawbacks.